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Description: F2812 SPI （CCS3.3开发环境下）实验说明:主要硬件部分：DSP，74HC595（串入并出的移位器),共阳数码管。SPIMOSI和SPICLK直接从DSP接到了74HC595的SER和SRCLK，作为数据和时钟信号的输入，SPISTE引脚接到了74HC595的RCLK以控制其选通。 实验结果:可看到数码管从0～F循环显示-F2812 SPI experiment shows: The main hardware components: DSP, 74HC595 (serial shifter in and out), common anode LEDs. SPIMOSI and SPICLK 74HC595 received directly from the DSP s SER and SRCLK, as the input data and clock signals, SPISTE 74HC595 received the RCLK pin to control the strobe. The results: You can see the LED display from 0 ~ F cycle
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Size: 342016 |
Author: 奋斗不止 |
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Description: 关于easy fpga开发板的led数码管的驱动；
--输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通，
-- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字
-- 控制时钟clk_dig一位用于时钟同步
--输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内；
-- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的；
--要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven
- Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe,
- Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display
- Control the clock for clock synchronization clk_dig a
- Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included
- Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode
- Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
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Size: 1024 |
Author: 陈伟峰 |
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Description: 关于easy fpga开发板的led数码管的驱动；
此为verilog程序
--输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通，
-- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字
-- 控制时钟clk_dig一位用于时钟同步
--输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内；
-- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的；
--要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven
This is a verilog program
- Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe,
- Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display
- Control the clock for clock synchronization clk_dig a
- Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included
- Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode
- Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
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Size: 1024 |
Author: 陈伟峰 |
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Description: 用STC的MCU的SPI方式控制74HC595驱动8位数码管。
用户可以修改宏来选择时钟频率, 可以修改寄存器定义是STC12C5A60S2系列 还是 STC12C5628AD STC12C5410AD STC12C4052AD系列.
用户可以在显示函数里修改成共阴或共阳.推荐尽量使用共阴数码管.
显示效果为: 8个数码管循环显示0,1,2...,A,B..F,消隐.-STC MCU SPI control 74HC595 to drive eight digital tube. User can modify the macro to select the clock frequency, you can modify the register definitions STC12C5A60S2 series or STC12C5628AD STC12C5410AD STC12C4052AD series. Display function, the user can modify the common cathode or common anode. Recommended to make use of a common cathode digital tube display: 8 The digital control loop to display 0, 1, 2 ..., A, B. F, blanking.
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Size: 68608 |
Author: 辉 |
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Description: 椭圆低通滤波器手册 MAX293 可以根据抗混时钟改变滤波F-Elliptic low-pass filter manual MAX293 clock change according to the anti-aliasing filter F
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Size: 324608 |
Author: zhangliang |
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Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
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Size: 600064 |
Author: 饕餮小宇 |
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Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
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Size: 607232 |
Author: 饕餮小宇 |
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Description: SD2400A/B/C/D/E/F 51汇编程序[2008/01/16]功能:读/写时钟,读写NVSRAM/EEPROM-SD2400A/B/C/D/E/F 51 assembler [2008/01/16] function: read/write clock NVSRAM read and write/EEPROM
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Size: 2048 |
Author: lei |
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Description: 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能，且数据ROM 在高速条件下，占用最少的逻辑资源，设计流程最便捷，波形数据获最方便。下图是此信号发生器结构图，顶层文件SINGT.VHD 在FPGA 中实现，包含2 个部分：ROM 的地址信号发生器，由5 位计数器担任，和正弦数据ROM，拒此，ROM由LPM_ROM模块构成能达到最优设计，LPM_ROM底层是FPGA中的EAB或ESB等。地址发生器的时钟CLK的输入频率f0与每周期的波形数据点数（在此选择64 点），以及D/A输出的频率f 的关系是：f=f0/64。-Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64.
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Size: 1825792 |
Author: 吴祥 |
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Description: 41、1602LCD简单时钟显示实验，按4X4键盘的 F键 进入设定状态 E D 键是前后移动键 C按键是调整数值按键 -1602 LCD clock display simple experiment 4X4 keypad press the F key to enter the setting status ED keys are keys to move around the C buttons are buttons to adjust the value
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Size: 2048 |
Author: DA |
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Description: 用定时器以间隔500MS在6位数码管上依次显示
0、1、2、3....C、D、E、F，重复。
设时钟频率为12M-500MS interval using the timer to display 0,1,2,3 .... C, D, E, F, repeat the sequence on 6 digital tube. Set the clock frequency is 12M
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Size: 1024 |
Author: xinfan |
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Description: 一个Java程序
• 时间(24小时时钟)噪声读数(您可能假设
用户输入一个整数范围在（0 . .23)
• 噪音分贝的音量(你可以假定用户将进入一个
整数范围在（0 . .200)
你的程序需要计算是否应该征收罚款,罚款的金额应该是什么。然后程序打印出罚款。
罚款的数量决定的
时间产生的噪声,噪声的响度。噪声在睡觉
时间(看作是10点或之后但在6点之前)被认为更严重
噪音在其他时间。睡眠时间以外,声音比90分贝噪音会增加
100美元的罚款。在睡觉期间,利率的有两种:如果噪音从70到
110分贝,罚款200美元,但如果是110分贝或更响亮,罚款300美元。
-Write a Java program called quest3.java that prompts for and reads in two integer
values:
• The hour (on a 24 hour clock) a noise reading is taken (you may assume the
user will enter an integer in the range 0..23, inclusive)
• The loudness of the noise in decibels (you may assume the user will enter an
integer in the range 0..200, inclusive)
Your program needs to calculate if a fine should be levied against the producers of the
noise, and what the amount of the fine should be. The program then prints out the fine.
The rules for determining the fine are as follows. The amount of a fine depends of the
time the noise was produced, and the loudness of the noise. Noise during sleeping
time (regarded as being 10pm or later but before 6am) is regarded more seriously than
noise at other times. Outside of sleeping time, a noise louder than 90 decibels incurs a
$100 fine. During sleeping time, there are two rates of fine: if the noise is from 70 up
to 110 decibels, the f
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Size: 1024 |
Author: ethan |
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Description: wireless thermometer:
server side- arduino mini pro+ dht22 + BH1750 lux meter+ DS1307 clock + optional 16x2 i2c LCD allready in the code
receiver side: 16x2 LCD... first row indoor temp in C and F a LM35 connected to pinA0, and RX rf 433mhz on pin 10
secound LCD display row: outdoot tem in C and Humidity in-wireless thermometer:
server side- arduino mini pro+ dht22 + BH1750 lux meter+ DS1307 clock + optional 16x2 i2c LCD allready in the code
receiver side: 16x2 LCD... first row indoor temp in C and F a LM35 connected to pinA0, and RX rf 433mhz on pin 10
secound LCD display row: outdoot tem in C and Humidity in
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Size: 7168 |
Author: aciduu |
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Description: 串行口扩展并行口实验,使用P1.0、P1.1作为74164串行输入数据线和时钟线，74164的输出接数码管的段码，P1.2接一位数码管的位选码，在一位数码管上轮流显示数字（0～F）。-Parallel port serial port expansion experiments, P1.0, P1.1 as 74164 serial input data and clock lines, connect the digital output of the segment code 74164, P1.2 bit by bit digital election code, turns display digital (0 ~ F) on a digital control.
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Size: 7168 |
Author: 林琳 |
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Description: Butterfly flying simulation
opengl achieve texture mapping te
Point cloud data were displayed,
OpenGL implementation model based
opengl an image production, dynam
The template code, can realize th
Opengl achieve the collision with
Use opengl draw cubes, and add ph
This is my car fire procedures, i
caculated passive Q-switch
Set up two sources, one is blue d
Use opengl draw cubes, cones, sph
A Computer Graphics Program on Tr
Devoted to OpenGL programming tec
A graphical clock, hour and minut
Unity3D terrain conversion code f
use OpenGL 3D painting of a ball
use OpenGL, prepared by the VC C,
OpenGL Super Bible eBook fourth.
Opengl realize the use of a simpl
VC++ Opengl realize the building
The sourcecode for OpenGL library
NeHe OpenGL tutorial, source code
Based on VC 6.0 and OpenGL achiev
An system which is based on OpenG
contains magic and inflating ball
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Size: 5120 |
Author: giang tuấ n |
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Description: 本文件是I2C总线时钟读写程序，使用外部22.1184MHz晶振.功能：为待机界面。按 A 键从时钟芯片读取当前时间，并在LCD上显示。按 F 返回显示待机界面。-
This document is read and write I2C bus clock, the use of an external crystal 22.1184MHz function: a standby interface. Press A button reads the current time the clock chip and displayed on the LCD. Press F to return the display standby interface.
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Size: 76800 |
Author: lfp |
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Description: 硬件平台：STM32F429I-DISCORVERY
软件平台：KEIL MDK5.10
在STM32F429I-DISCO board中，由于串口2被L3GD20和液晶数据线占用，所以串口1很方便，而且还留了2个孔外接。
* 说 明 : 实现printf和scanf函数重定向到串口1，即支持printf信息到USART1
* 实现重定向，只需要添加2个函数:
* int fputc(int ch, FILE *f)
* int fgetc(FILE *f)
* 对于KEIL MDK编译器，编译选项中需要在MicorLib前面打钩，否则不会有数据打印到USART1。
- This example describes how to use the ADC3 and DMA to transfer continuously
converted data ADC3 to memory.
The ADC3 is configured to convert continuously channel13.
Each time an end of conversion occurs the DMA transfers, in circular mode, the
converted data ADC3 DR register to the ADC3ConvertedValue variable.
To get the maximum ADC performance (2.4 MSPS, at 2.4V to 3.6V supply range),
the ADC clock must be set to 36MHz. As ADC clock is equal to APB2/2, then APB2
value will be 72MHz which lead to maximum AHB (System clock) at 144MHz.
Since the sampling time is set to 3 cycles and the conversion time to 12bit data
is 12 cycles, so the total conversion time is (12+3)/36= 0.41us(2.4Msps).
The converted voltage is displayed on the STM32F429I-DISCO board LCD (when the define USE_LCD
is enabled in main.h). It can also be monitored by adding the variable ADC3ConvertedValue
to the debugger watch window.
@par Example Description
This example is
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Author: |
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Description: Multirate digital signal processing system which includes
sampling rate conversion. This technique is necessary for
systems with different input and output sampling rates, as the
proposed multirate device is downsampler FPGA
implementation of the same is presented. The FPGA synthesis
results are verified and report is presented. In order to build
down sampler consisting of D F/F and clock generator, are
downloaded on cyclone-II FPGA-Multirate digital signal processing system which includes
sampling rate conversion. This technique is necessary for
systems with different input and output sampling rates, as the
proposed multirate device is downsampler FPGA
implementation of the same is presented. The FPGA synthesis
results are verified and report is presented. In order to build
down sampler consisting of D F/F and clock generator, are
downloaded on cyclone-II FPGA
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Size: 2048 |
Author: Mohan Reddy |
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Description: f(n)=f(n-1)+f(n-2) f(0)=f(1)=1，求斐波那契数列第20项，分别用循环和递归的方式，比较时间效率。提示：可以使用c函数clock取出当前系统时间，计算前后各一次，两次相减除以每秒的时钟数，就可以得到以秒为单位的差距-f (n) = f (n-1)+ f (n-2) f (0) = f (1) = 1, Item 20 seeking Fibonacci number Fibonacci sequence that were circulating and recursively, more time effectiveness. Tip: You can use the c function Remove the current system clock time, before and after the calculation each time, twice per second relative to the clock deduction, you can get in seconds gap
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Size: 2542592 |
Author: 龙晓聪 |
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Description: 本实验的目的是通过请求页式存储管理中页面置换算法模拟设计, 了解虚拟存储技术的特点, 掌握请求页式存储管理的页面置换算法。
①先进先出的算法( F I F O ) ;
②最近最少使用算法( L R U ) ;
③最佳淘汰算法( O P T ) : 先淘汰最不常用的页地址;
④最少访问页面算法( L F U ) ;
⑤简单时钟算法( CLOCK）(Page replacement algorithm)
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Size: 21504 |
Author: suprelee
|
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